The present invention relates to improvement of a semiconductor integrated circuit, particularly, a decode circuit for use in a DRAM, a flash memory or the like. More particularly, it relates to operation speed increase and power consumption decrease in a logic circuit in which an input order of signals is previously determined.
In accordance with recent spread of portable equipment and in view of energy-saving, there are increasing demands for decrease of power consumption of LSIs. In order to decrease the power consumption, decrease of a supply voltage is effective. Moreover, in accordance with refinement of transistors, the decrease of a supply voltage has become indispensable in the design of LSIs for attaining reliability thereof. However, when the supply voltage is decreased, the driving ability of a transistor is degraded. As a result, necessary performance as an LSI cannot be attained. A driving current Id for a transistor is substantially obtained as follows : EQU Id=.beta..multidot.(Vgs-Vt).sup.2
Therefore, as a threshold voltage Vt decreases, the driving ability of the transistor is improved. For example, in the case where the supply voltage is 1.0 V and a voltage of 1.0 V is applied as a gate-source voltage Vgs, the driving ability of the transistor can be substantially doubled by decreasing its threshold voltage Vt from 0.5 V to 0.3 V. However, when the threshold voltage is decreased, there is a possibility of a leakage current, and hence, the threshold voltage of the transistor included in a circuit cannot be simply decreased.
Accordingly, as a conventional method of attaining both a high operation speed and a small leakage current, an MTCMOS circuit has been proposed as disclosed in, for example, Japanese Laid-Open Patent Publication No. 6-29834. Now, application of this MTCMOS circuit to a decode circuit for a memory will be exemplified.
This decode circuit comprises a plurality of circuit blocks including a large number of logic circuits connected with one another in parallel. Each circuit block is connected with a power line through a P-type MOS transistor having a high threshold voltage, and is connected with a ground line through an N-type MOS transistor having a high threshold voltage. The respective P-type and N-type MOS transistors having the high threshold voltage in each circuit block are commonly controlled in accordance with two operation/standby switching signals complementary to each other.
Therefore, during a standby, the two MOS transistors having the high threshold voltage are in an off-state in accordance with the operation/standby switching signals in each circuit block, so that each circuit block can be disconnected from the power line and the ground line. Thus, a leakage path from the power line to the ground line through each circuit block can be effectively cut off by using the high threshold voltages of the MOS transistors, resulting in decreasing a leakage current. On the other hand, during an operation, the two MOS transistors having the high threshold voltages are in an on-state in accordance with the operation/standby switching signals in each circuit block, so that the power line and the ground line can be connected with each circuit block. Thus, the logic circuits in each circuit block can be operated. At this point, when the logic circuits in each circuit block include transistors having a low threshold voltage, each of the transistors has high driving ability owing to its low threshold voltage, and hence can be operated at a high speed. In this manner, both a high operation speed during an operation and a low leakage current during a standby can be attained.
In the conventional decode circuit, however, although a leakage current can be suppressed during a standby, both the P-type and N-type MOS transistors having the high threshold voltages are required. Therefore, the area of the resultant circuit is increased because these transistors are hierarchically inserted.
Furthermore, when the threshold voltage of the transistor having the high threshold voltage is set at an excessively large value for the purpose of decreasing a leakage current, the driving ability of the transistor having the high threshold voltage can be degraded. As a result, even when each of the transistors in the logic circuits has a low threshold voltage, the high speed operation performance of the logic circuits can be spoiled by the transistor having the high threshold voltage. Therefore, the high threshold voltages of the P-type and the N-type MOS transistors are set in a range where a low leakage current during a standby and a high speed operation of the circuit can be attained, and hence, excellent results cannot be expected in both objects.
Moreover, in the conventional decode circuit for a memory, when a predetermined one circuit block is selected during an operation, one of the logic circuits is selected in the selected circuit block, so that the output of the selected logic circuit is used as a decode signal. However, in each of the other plural circuit blocks (namely, unselected circuit blocks) excluding the selected circuit block including the selected logic circuit outputting the decode signal, the two MOS transistors having the high threshold voltage are in an on-state in accordance with the operation/standby switching signals. Therefore, the unselected circuit blocks are connected with the power line and the ground line, so as to form a leakage path in each of these unselected circuit blocks and allow a leakage current to flow. In this manner, the conventional decode circuit has a disadvantage of a large leakage current in the unselected circuit blocks during an operation.